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fairmont hotel : V. K. Agarwal, McGill Univ., Canada M. Rivier, IBM, FranceL. R. Carley, CMU, USA M. Sami, Politecnico di Milano, ItalyA. V. Ferris-Prabhu, IBM, USA G. Saucier, INPG, Grenoble, FranceW. K. Fuchs, Univ. of Illinois, USA Y. Savaria, Ecole Polytechnique, CanadaV. K. Jain, Univ. South Florida, USA C. H. Stapper, IBM, USAI. Koren, Univ. of Massachusetts, USA E. Swartzlander, Univ. of Texas, USAR. M. Lea, Brunel Univ., UK J. P. Teixeira, INESC, PortugalF. Lombardi, Texas A&M Univ., USA J. Trihle, SGS Thomson, FranceT. Mangir, TRW, USA T. W. Williams, IBM, USAW. Moore, Oxford, UKThe workshop will be held at Hidden Valley Resort, in the Laurel Mountains,a one-hour drive east of Pittsburgh, Pennsylvania. The resort has golfcourses, hiking trails, tennis courts, indoor swimming pool, fitness center,and downhill and cross-country skiing trails.USAir is providing special fares to workshop participants for travel to andfrom Pittsburgh between November 16-22, 1991; 5% off published USAirpromotional round trip fares in the Continental U.S. or 35% off full roundtrip day coach fares, some exclusions apply. There are similar discountsfor travel from Canada. For reservations, call USAir at (800) 334-8644 inthe Continental U.S. and (800) 428-4322 (x7702) in Canada. Refer to "GoldFile" Number 45650004.
fairmont hotel : Driving from the Greater Pittsburgh International Airport: exit the airporttoward Pittsburgh on Route 60 South. Route 60 becomes Interstate 279.Follow I-279 to I-376 East, to the Pennsylvania Turnpike. Take the TurnpikeEast to Exit 9, Donegal. Turn left onto Route 31 East and follow the signs.Hidden Valley is on the right about 8 miles from the exit, and about onemile past the summit of Laurel Mountain. Driving time is about 90 minutes.Shuttle Van: Hidden Valley will provide shuttle vans between the Pittsburghairport and the resort. Shuttles cost $40 each way per person for Sundayarrivals. For other days, the van is $58 for 1, $40 for 2, and $34 for 3+persons. If you want to take the shuttle, you must indicate this on thehotel reservation form and call Hidden Valley at (814) 443-6454 to confirmyour flight arrival time before November 10.Conference registration includes admission to all tutorials and sessions,and a copy of the proceedings. Guest registration includes all meals,refreshments, breaks and use of resort amenities. Please return the hotelreservation form to Hidden Valley by October 28. A limited number of eachroom type is available. Requests will be filled on a first-come basis.After October 28, please call Hidden Valley at (813) 443-6454 forreservations. Reservations must be guaranteed by a first night deposit,refundable if canceled by 4:00pm on the intended arrival date. Pleasereturn the workshop registration form to the Registration Chair by November1.
fairmont hotel : Monday 11/1807:00-08:30a Breakfast/Registration08:30-09:00a Welcome - W. Maly, D. M. H. Walker, S. W. Director, Carnegie Mellon University09:00-10:00a Session 1 - Tutorial 1 - Wojciech Maly Optimization of Parametric Yield, S. W. Director, Carnegie Mellon University10:00-10:30a Break10:30-12:00p Session 2 - Architecture - Earl Swartzlander State-of-the-Art of the Wafer Scale ELSA Project, A. Boubekeur, J. L. Patry, G. Saucier, J. Trihle, INPG, SGS Thomson Wafer-Scale Massively Parallel Computing Modules for Fault- Tolerant Signal and Data Processing. R. M. Lea, Brunel Univ. Defect Tolerance and Yield for a WSI Rapid Prototyping Architecture, V. K. Jain, D. C. Keezer, Univ. South Florida Current-Mode Approach for Analog VLSI: Technology Issues and Defect Tolerance, A. G. Andreou, Johns Hopkins Univ. Circuit Design for a Large Area High-Performance Crossbar Switch, M. Patyra, W. Maly, Carnegie Mellon University12:00-01:30p Lunch01:30-03:00p Session 3 - Fault/Yield Models 1 - Israel Koren Improved Yield Models for Fault-Tolerant Random Access Memory Chips, C. H. Stapper, IBM Applications of a Mechanistic Yield Model for MOS IC Chips, C. M. Drum, AT&T Circuit-Level Modeling of Spot Defects, D. Gaitonde, D. M. H. Walker, Carnegie Mellon University Knowledge-Based Electrical Monitor Approach Using Very Large Array Yield Structures to Delineate Defects During Process Development and Production Yield Improvement, J. Hammond, G. Sery, Intel03:00-03:30p Break03:30-05:00p Session 4 - Fault/Yield Models 2 - Vijay Jain A Model for Enhanced Manufacturability of Defect Tolerant ICs, Z. Koren, I. Koren, University of Massachusetts, Amherst Harvest Rate of Reconfigurable Pipelines, W. Shi, M. F. Chang, W. K. Fuchs, University of Illinois, Urbana Neural Networks on Silicon: The Mapping of Hardware Faults onto Behavioral Errors, M. Sami, R. Stefanelli, V. Piuri, Politecnico di Milano05:00-06:00p Free Time06:00-08:00p Dinner08:00-10:00p Discussion Groups - Defect/fault modeling - Is functional or parametric yield more important? - Is there a future for defect tolerance?
fairmont hotel : Tuesday 11/1907:00-08:30a Breakfast08:30-09:30a Session 5 - Tutorial 2 - Wojciech Maly Monolithic vs. MCMs, a Perspective on Performance, Yield and Manufacturing Concerns, Bill Siu, Intel09:30-10:00a Session 6 - Fault Tolerance 1 - Vinod Agarwal Key Issues in the Design of a Fault-Tolerant Core Avionics Computer Based on a Mesh Architecture, A. Nordsieck, Boeing Overview of Fault Handling for the Chaos Router, K. Bolding, L. Snyder, University of Washington10:00-10:30a Break10:30-12:00p Session 7 - Fault Tolerance 2 - Vinod Agarwal Effects of Fault Tolerance on the Reliability of Memory Array Supports, F. J. Aichelmann, IBM Concurrent Error Diagnosis in Mesh Array Architectures based on Overlapping H-Processes, E. Manolakos, D. Dakhil, M. Vai, Northeastern University Evaluation of FUSS and Other Reconfiguration Schemes, N. Lopez-Benitez, M. Chean, Louisiana Tech A New Approach to Modeling the Performance of a Class of Fault Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy Y. Y. Chen, S. J. Upadhyaya, SUNY Buffalo12:00-01:30p Lunch01:30-03:00p Session 8 - Test 1 - Tom Williams On the Modeling and Testing of Gate Oxide Shorts in CMOS Logic Gates, H. Hao, E. J. McCluskey, Stanford University On the Testability of Realistic Bridging Faults, M. B. Santos, J. J. H. T. de Sousa, F. M. Goncalves, J. P. Teixeira, INESC Physical Fault Injection: A Suitable Method for the Evaluation of Functional Test Efficiency, R. Velazco, B. Martinet, IMAG A Bottom-Up Methodology to Characterize Delay Faults, J. Zubairi, G. L. Craig, Syracuse University Delay Fault Simulation of Self-Checking Error Checkers, K. Hirabayashi, Toshiba03:00-03:30p Break03:30-05:00p Session 9 - Test 2 - Ed McCluskey Almost Sure Diagnosis of Almost Every Good Element, K. Huang, L. E. LaForge, V. K. Agarwal, McGill University A Method for the Consistent Reporting of Fault Coverage, W. Debany, K. Kwiat, S. Al-Arian, USAF, Univ. South Florida Concurrent Built-In Self-Test with Reduced Fault Latency, Y. N. Shen, F. Lombardi, Texas A&M University Array Architecture for ATG with 100% Fault Coverage, K. El-Ayat, R. Chan, C. L. Chan, T. Speers, Actel05:00-06:00p Free Time06:00-08:00p Dinner08:00-11:00p Discussion Groups - Wafer scale integration versus multi-chip modules - Status and future of fault tolerance - Status and future of built-in self-test - Future workshop directions
fairmont hotel : Wednesday 11/2007:00-08:30a Breakfast08:30-09:30a Session 10 - Tutorial 3 - Wojciech Maly Physical Limits of Performance: The Interconnection Perspective, S. Tewksbury, University of West Virginia09:30-10:00a Session - Reconfiguration 1 - Yvon Savaria Efficient and Optimal Fault-to-Spare Assignments in Doubly Fault Tolerant Arrays, R. Melhem, N. Shrivastava, Univ. Pittsburgh10:00-10:30a Break10:30-12:00p Session 11 - Reconfiguration 2 - Yvon Savaria Fast Search Algorithms for Reconfiguration Problems, R. Libeskind-Hadas, C. L. Liu, University of Illinois, Urbana Reconfiguration of Time-Multiplexed Binary Trees for Satellite Communication, K. Raghunandan, F. P. Coakley, Univ. of Surrey Hex-Repair: A New Approach to Hexagonal Array Reconfiguration, R. Venkateswaran, P. Mazumder, K. G. Shin, Univ. of Michigan Some Results and Open Problems Concerning Memory Reconfiguration Under Clustered Models, D. Blough, A. Pelc, UC Irvine, Univ. Quebec, Hull12:00-01:30p Lunch===============================Cut Here==================================== ===First Name: _____________________ Last Name: _________________________________Company /Institution: ________________________________________ _________________Address: ________________________________________ _____________________________City: ________________ State/Province: ____ Postal Code: ______ Country: _____E-mail: ______________________________ Phone: _____________ Fax: _____________Circle Fee Before Nov. 1, 1991 After Nov. 1, 1991IEEE Member US$205 US$245Non-member US$260 US$305IEEE Member No. __________________________Payable by check or money order in U.S. dollars.Make checks payable to "IEEE Int'l Workshop onDefect and Fault Tolerance in VLSI Systems".
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